Low-power, low-voltage four-quadrant analog multiplier, particularly for neural applications
US5805007A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 1996 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Sep 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/163
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiplier presenting four multiplying branches, each formed by a buffer transistor and by two input transistors arranged in series to one another and connected between two output nodes and a common node. A biasing branch presents a diode-connected forcing transistor with its gate terminal connected to the gate terminal of all the buffer transistors, and its source terminal connected to the common node. The forcing transistor forces the input transistors to operate in the triode (linear) region, i.e., as voltage-controlled resistors, so that they conduct a current linearly proportional to the voltage drop between the respective source and gate terminals, and the currents through the output nodes are proportional to the input voltages applied to the control terminals of the input transistors. By cross-coupling the multiplying branches to the output nodes and subtracting the two output currents, a current is obtained which is proportional to the product of the two input voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.