Enhanced signal integrity bus having transmission line segments connected by resistive elements
US5805030A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 1995 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Aug 4, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10022
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An arrangement in which resistors are interposed on a bus line to attenuate reflected spurious pulses. The resistors are positioned on the bus so as not to be between a processor and its cache memory, but so as to be between the combination of the processor and cache memory and components such as a peripheral controller and a memory controller. The resistors reflect a portion of the pulse energy and attenuate the pulse energy passing through them. In another aspect of the invention, the traces making up the bus are arranged so that the intertrace distance is greater than a distance between the traces and an internal reference plane. This causes magnetic energy radiated by an aggressor trace to encounter the reference plane before it encounters a victim trace. This also reduces the amount of magnetic cross-coupling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.