Two's complement digital to analog converter
US5805095A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 1997 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Jan 10, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A two's complement digital to analog converter (300) is for converting a two's complement binary value to an analog output current, and includes a control circuit (310) which generates controlled value bits, a digital to analog current converter (DACC) (320), and an augmenter (330). The DACC (320) generates a DACC analog current which is a portion of the analog output current and which has an absolute value which is related to the binary value of the controlled value bits. The augmenter (330), which is coupled to a most significant bit of the two's complement binary value, generates a portion of the analog output current by modifying the absolute value of the DACC analog current by a least significant bit current increment when the most significant bit indicates a negative value of the two's complement binary value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.