Verification of instruction and data fetch resources in a functional model of a speculative out-of order computer system
US5805470A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 10, 1996 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Oct 10, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for verifying the correct behavior of instruction and data fetches and the order of instruction and data fetch resource modifications by a speculative and or out-of-order computer architecture under test is presented. An architectural model which models the high-level architectural requirements of the computer architecture under test, including instruction fetch resources and data fetch resources, executes test stimuli instructions in natural program order. A behavioral model, which models the high-level architectural requirements of the computer architecture, including instruction fetch resources and data fetch resources, executes the same test stimuli instructions, but according to the speculative and or out-of-order instruction execution behavior defined by the computer architecture under test. Modifications to instruction fetch resources and data fetch resources by the behavioral model are respectively recorded separately in a respective instruction fetch resource event queue and data fetch resource event queue. Upon detection of a fetch instruction event by the behavioral model, each instruction fetch resource event stored in the instruction fetch resource …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.