Inverse discrete cosine transform processor having optimum input structure
US5805482A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 20, 1995 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Oct 20, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An inverse discrete cosine transform processor for transforming a video signal from frequency domain signals into spatial domain signals. A bus converter receives DCT coefficient data from parallel processing paths and converts the DCT coefficient data to even and odd processing paths. Partial IDCT processors convert, in parallel, the coefficient data from the even and odd processing paths to produce intermediate coefficient values by performing a one dimensional transform. The intermediate coefficient values are transposed in a transpose RAM to produce transposed intermediate coefficient values which are subsequently separated into even and odd processing paths and converted in parallel to produce pixel values by performing a one dimensional transform. The 1-D IDCT processors each include input section circuits which each receive four-bits of 12-bit or 16-bit input values and provides one bit of each of four input values in a four clock cycle time period. Each of the 1-D IDCT processors also includes an accumulator section which includes adders which sum M-1 bit values to produce an M-bit output value. Any bits of less significance than the M-1 input values are applied to carry lo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.