Four device SRAM cell with single bitline
US5805496A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 1996 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Dec 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a static inverter having an input connected to a storage node. An impedance connects the storage node to a voltage supply. A first transistor, having an input connected to an output of the static inverter, connects the storage node to a write line. Lastly, a second transistor, responsive to a wordline access signal, connects the storage node to a single data bitline. The memory cell further includes a single ended four transistor CMOS SRAM cell. Additionally, a memory array is disclosed which includes a plurality of memory cells arranged to form a matrix of rows and columns, each memory cell including a single ended four transistor CMOS SRAM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.