Semiconductor static random access memory cell with additional capacitor coupled to memory nodes and process of fabrication thereof
US5805497A · kind A · utility
7Cited by
2References
7Claims
0Family size
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Key dates
| Filing date | Mar 27, 1997 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Mar 27, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A semiconductor static random access memory cell is implemented by four field effect transistors formed on a silicon layer over a buried silicon oxide layer and two resistors formed in an inter-level insulating structure; additional capacitors are formed under the buried silicon oxide layer, and are respectively connected to the gate electrodes of the field effect transistors serving as driving transistors of the memory cell so as to enhance the stability of the memory cell without increase the transistor size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.