Real time parser for data packets in a communications network
US5805808A · kind A · utility
80Cited by
12References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 9, 1997 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Apr 9, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A parser for reading bits of a packet has a set of logic circuits implemented in a computer chip; a memory interacting with the computer chip, the memory providing first data to the set of logic circuits; means for reading bits from any field of packet into the set of logic circuits, the bits providing second data to the set of logic circuits; means, responsive to the first data and the second data, for the logic circuits to interpret bits of the packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.