Method and system for reducing average branch resolution time and effective misprediction penalty in a processor
US5805876A · kind A · utility
26Cited by
7References
30Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 30, 1996 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Sep 30, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Logic circuitry provides a fast resolution of conditional branch instructions in a high-performance superscalar processor. The logic circuitry facilities early (fast) resolution of a subset of conditional branches located within the first position of the primary instruction buffer within the processor enabling the overall branch processing logic to bypass history table-based prediction logic for such branches without crossing the cycle boundary. Thus, penalties associated with possible mispredictions for this subset of conditional branches are avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.