Data processor with branch target address cache and method of operation
US5805877A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1996 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Sep 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor (10) has a BTAC (48) storing a number of recently encountered fetch address-target address pairs. A branch unit (20) generates a fetch address that depends upon a condition precedent and a received branch instruction. After executing each branch instruction, the branch unit predicts whether the condition precedent will be met the next time it encounters the same branch instruction. If the predicted value of the condition precedent would cause the branch to be taken, then the branch unit adds the fetch address-target address pair corresponding to the branch instruction to the BTAC. If the predicted value of the condition precedent would cause the branch to be not taken, then the branch unit deletes the fetch address-target address pair corresponding to the branch instruction from the BTAC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.