Queued serial peripheral interface having multiple queues for use in a data processing system
US5805922A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | May 2, 1994 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | May 2, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Serial communication circuitry (10) having multiple queues (11-14) for use in a data processing system (95). Each queue (11-14) has multiple entries (52). Serial transfers from the multiple queues (11-14) are carried out under the control of global parameters (e.g. 205, 209), per-queue parameters (e.g. 211-212, 214-217), and per-entry parameters (e.g. 350-361). Each queue can be programmed to have a different set of per-queue parameters, and each entry within a queue can be programmed to have a different set of per-entry parameters. In addition, serial communication circuitry (10) can perform serial data transfers in response to the assertion of a trigger signal (30) from a source such as a timer (63) or a central processing unit (61). As a result, data transfers can be more precisely related to a particular timing signal or set of timing signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.