Multiprocessor memory controlling system associating a write history bit (WHB) with one or more memory locations in controlling and reducing invalidation cycles over the system bus
US5806086A · kind A · utility
21Cited by
1References
6Claims
0Family size
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Key dates
| Filing date | Jun 11, 1996 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Jun 11, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2542
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller system for use with a plurality of processor nodes capable of reducing the number of invalidate cycles on a shared system bus in cache coherent non-uniform memory architecture multiprocessor by detecting when a memory block is being updated by multiple nodes and requesting exclusive access for any read of the actively updated data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.