Row decoder with level translator
US5808482A · kind A · utility
9Cited by
16References
43Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 13, 1997 |
| Grant date | Sep 15, 1998 |
| Priority date | — |
| Expiry date | Mar 13, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A combined row decoder and level translator powered by an on-chip high voltage supply results in an efficient layout, area savings and elimination of the global precharge signal resulting in additional area and power savings. In addition, power from the high voltage supply is consumed only by the level translator and wordline driver of the selected decoder resulting in additional power savings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.