Parallel micro-relay bus switch for computer network communication with reduced crosstalk and low on-resistance using charge pumps
US5808502A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Mar 26, 1996 |
| Grant date | Sep 15, 1998 |
| Priority date | — |
| Expiry date | Mar 26, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A micro-relay replaces electromechanical and solid-state opto-isolated relays in a computer network. The micro relay is an integrated circuit containing several bus switches in parallel. Each bus switch can make or break a connection. The bus switch is an n-channel MOS transistor with the source and drain connected to different network busses. A bus enable input causes the connection to be made or broken. The bus enable input is separately buffered for each gate of each MOS transistor to prevent crosstalk between bus switches. Since the MOS transistor stops conducting when the source is at a voltage level of the power-supply voltage minus the threshold voltage, a boosted voltage is applied to the gate of the MOS transistor to allow conduction even when the source is at the power-supply voltage level. The boosted voltage is generated by a charge pump. A substrate bias is applied to the transistors to prevent crosstalk from undershoots. Buffers for the gates of the bus switches are inverters that are connected to the boosted voltage rather than the power supply, and to the substrate voltage rather than ground. Thus the gates are driven to the boosted voltage or to the substrate volta…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.