Multichip package having exposed common pads
US5808877A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 1996 |
| Grant date | Sep 15, 1998 |
| Priority date | — |
| Expiry date | Sep 19, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multichip package having individual chips which can be tested at the package level. A first pattern of conductive wires is formed on an upper surface of the circuit board for electrically connecting the individual chips. A second pattern of conductive wires is formed on the upper surface of the circuit board for providing data connections between the individual chips. Common pads formed in the circuit board extend from the upper surface to a lower surface of the circuit board, and the second patten of conductive wires is connected via the common pads. A molding compound is formed over the upper surface of the circuit board, embedding the individual chips and the first and second conductive patterns, while leaving the lower surface of the circuit board and a lower surface of the common pads exposed. A test socket having pad contact pins corresponding to the locations of the common pads, is placed at the lower surface of the circuit board so that signals may be applied and detected at common pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.