Reconfiguring control system in a parallel processing system by replacing an error-detected processing unit
US5808886A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 14, 1995 |
| Grant date | Sep 15, 1998 |
| Priority date | — |
| Expiry date | Mar 14, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/06
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A sender processor unit 101 transmits a packet to which a logical address of a receiver processor unit is added. Network routers 102 to 108 obtains a physical address corresponding to a destination logical address by referring to a processor address translation table 122 through a signal line 140, sets a route 112 and transfers the packet to a receiver processor unit 107. When a fault is caused in the receiver processor unit 107, a service processor changes correspondence of logical addresses to physical addresses of the processor address translation table 122. Consequently, a route 113 to a substitute processor unit 105 is dynamically
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.