Memory having direct strap connection to power supply
US5808900A · kind A · utility
15Cited by
15References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1996 |
| Grant date | Sep 15, 1998 |
| Priority date | — |
| Expiry date | Apr 30, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory layout definition for connection to a power supply bus in an integrated circuit layout pattern. The layout definition includes an outline and a plurality of power supply conductor segments within the outline. At least one of the power supply conductor segments has a direct strap identifier which indicates a desired attachment to the power supply bus. The direct strap identifier is passed to a routing design tool which routes a direct strap conductor from the power supply bus to the power supply conductor segments having the direct strap identifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.