Semiconductor memory and method of manufacturing the same
US5808943A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 1996 |
| Grant date | Sep 15, 1998 |
| Priority date | — |
| Expiry date | May 3, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory, such as Dynamic Random Access Memory (DRAM), is provided for replacing a defective memory cell with a spare memory cell. The DRAM includes a main section which has a memory cell array with a plurality of memory cells arranged in an array. A spare section having a spare memory cell array also includes a plurality of memory cells arranged in an array. An address decoder specifies addresses, respectively, of the main section array and the spare section array. A defective bit replacement control circuit is connected to the address decoder and includes a plurality of electrically rewritable nonvolatile memory cells. The address decoder conducts a change-over operation for specifying an address of the first or second arrays according to a storage state, i.e., contents, of electrically rewritable nonvolatile memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.