Internal clock generating circuit for clock synchronous type semiconductor memory device
US5808961A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 25, 1997 |
| Grant date | Sep 15, 1998 |
| Priority date | — |
| Expiry date | Jul 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An internal clock signal generation circuit includes a portion to generate an internal clock signal (intCLK) generated in synchronization with an external clock signal, a pulse width setting circuit which sets the pulse width of the internal clock signal depending the operation condition. By adjusting the pulse width of the internal clock signal to generate depending upon the operation condition, an internal clock signal having an optimum pulse may be readily generated. An internal clock signal having an optimum pulse width depending upon the operation condition may be generated accordingly, and internal data may be accurately transferred as a result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.