Multi-level computer cache system providing plural cache controllers associated with memory address ranges and having cache directories
US5809525A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 1996 |
| Grant date | Sep 15, 1998 |
| Priority date | — |
| Expiry date | Jun 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0822
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hierarchical cache system comprises first and second pluralities of data caches and first and second respective higher level caches. The first higher level cache is coupled to the first plurality of caches and stores data of the first plurality of caches. The second higher level cache is coupled to the second plurality of caches and stores data of the second plurality of caches. First and second storage controllers access first and second respective address ranges from a main memory and the higher level cache subsystems. The first higher level cache responds to a request for data not contained in the first higher level cache by determining which of the address ranges encompasses the requested data and forwarding the request to the storage controller which can access the determined address range. The second higher level cache responds to a request for data not contained in the second higher level cache by determining which of the address ranges encompasses the requested data and forwarding the request to the storage controller which can access the determined address range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.