Method and apparatus for real memory page handling for cache optimization
US5809561A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1996 |
| Grant date | Sep 15, 1998 |
| Priority date | — |
| Expiry date | Oct 7, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/653
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved method and apparatus for managing real pages, also called physical pages, and virtual pages, also called logical pages, in a virtually indexed cache that is implemented as two physical caches. A list of free real pages that is a doubly linked list with a single anchor in addition to the free real pages is created. The pages are sequentially associated with each other using two sets of pointers. A set of forward pointers are used with the first pointer connecting the anchor page to the first physical page in the list and subsequent pointers connecting subsequent pages with each other with the last page having a pointer pointing to the anchor page. A set of backward pointers are employed with the first pointer pointing from the anchor to the last page in the list with subsequent pointers traversing the list towards the first page with the first page having the last pointer pointing to the anchor page. When a request for a real page is received to assign to a virtual page, an identification of whether the virtual page is an even or odd virtual page is made. The last real page in the list is assigned in response to a determination that the virtual page is an even virtual pa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.