Method for fabricating silicon-on-insulator device wafer
US5810994A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1996 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Oct 3, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76251
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A silicon on-insulator device wafer having a very thin monocrystalline film with uniform thickness. It is fabricated by vias technique in which a monocrystalline silicon film on an insulator is etched with a base silicon etching solution in an etch apparatus by applying a vias in such a way that the solution may serve as an anode and the substrate of SOI structure as a cathode. The presence of the insulator generates vacancies in a lower region of the monocrystalline silicon film and electrons in the substrate, so that the lower region charged with the vacancies is not removed by the base silicon etching solution, thereby leaving a highly uniform, thin monocrystalline silicon film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.