Semiconductor chip package device having a rounded or chamfered metal layer guard ring
US5811874A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 11, 1997 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Apr 11, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip packaging device includes a lead frame electrically connected to the chip and mechanically supporting the chip; a metal layer guard ring formed along at least one peripheral edge of an active surface of the chip; at least one slit formed at corner parts of the chip; a passivation layer covering the metal layer guard ring, the chip and the lead frame; and a package body made of a molding resin encapsulating the passivation layer, the lead frame, the metal layer and the chip; the metal layer guard ring being chamfered or rounded at corner parts of the chip to reduce shear stresses at the corner parts of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.