Power converter having switching frequency phase locked to system clock
US5811999A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 1996 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Dec 11, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B15/04
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A circuit for synchronizing a periodic ramp signal utilized in a switching mode power converter to system clock signal. A capacitor is charged through a resistor. When a voltage across the capacitor reaches a predetermined level, the capacitor is discharged and the charging cycle is repeated, thereby generating the periodic ramp signal across the capacitor. A waveform shaping circuit shapes the ramp signal into a rectangular wave signal having a same frequency and phase as the ramp signal. A phase comparator compares a phase of the rectangular wave signal to a phase of the system clock signal for forming a phase error signal. The phase error signal controls a level of current supplied to the timing capacitor by a voltage controlled current source. When the frequency of the system clock signal is higher than the frequency of the ramp signal, the phase comparator causes the voltage controlled current source to supply additional current to the capacitor, increasing the frequency of the ramp signal. When the frequency of the system clock signal is lower than the frequency of the ramp signal, the phase comparator causes the voltage controlled current to supply less current to the capaci…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.