Differential amplifier circuit having low noise input transistors
US5812022A · kind A · utility
12Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 1996 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Sep 18, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45076
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A differential amplifier circuit whose noise is reduced when used in a CMOS operational amplifier without increasing its cost includes a differential input stage circuit in which gate lengths of load transistors and gate lengths of differential input transistors are set to an optimal ratio to minimize internal transistor noise components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.