Redundancy circuit and method for providing word lines driven by a shift register
US5812465A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 1996 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Aug 2, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention disables defective rows in a FIFO or other buffer where the word lines of the FIFO buffer are driven by a shift register scheme. Additional enabled rows may be placed within the normal memory array. The additional enabled rows are substituted, as needed, for one or more defective rows. As a result, a defective row can be disabled without effecting the operation of the FIFO, particularly the read or write data path. In one example, the disabling effect is achieved by using one or more laser fuses. The present invention can be used to effectively bypass any single shift register element or a multiple number of shift register elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.