Synchronization and battery saving technique
US5812617A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1994 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Dec 28, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A synchronization apparatus in a selective call receiver comprised of a digital variable bandwidth phase locked loop with means to simultaneously detect the synchronization code word, means to generate a binary code from a register representative of lock quality, means to increment or decrement the lock quality register, means to sum the lock quality binary code into a phase error register, whereby the polarity of the sum is controlled by a phase comparison of the a local clock with the received data, and whereby the under or over flow of the phase error register determines the direction of a phase adjustment to the local bit clock generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.