System for transmitting data packet from buffer by reading buffer descriptor from descriptor memory of network adapter without accessing buffer descriptor in shared memory
US5812774A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 1997 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Jan 6, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/387
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The problems of meeting tight latency requirement while keeping network design low in cost and complexity are solved by the present invention of a network controller with a transaction logic block and a descriptor memory. The invention allows the data buffers and the buffer descriptors to be located in two physically separate memory subsystems. Data buffers can reside in a main system memory which are shared by other system clients. The buffer descriptors, which typically require significantly less memory space than data buffers, can reside in a special dedicated memory which can be low cost. The invention provides a method to allow buffer descriptors to be located in a low latency memory, which can be local to the network adapter. The data buffers can be located in a system shared memory. This design allows system shared resources, e.g. main system memory or bus, to be designed with relatively longer delay budget. This provides a significant system benefit since the buffer memory size is typically many orders of magnitude larger than the buffer descriptor memory size. The invention also provides a method where a system bus supports a priority service where low latency is guarantee…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.