Support structures for an intelligent low power serial bus
US5812796A · kind A · utility
65Cited by
3References
51Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 18, 1995 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Aug 18, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. Each peripheral device includes a plurality of serial bus support structures. For example, the serial bus support structures can include an interrupt generation circuit, a power-on circuit, and a wake-up interrupt generation circuit, and a wake-up interrupt propagation circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.