Executing speculative parallel instructions threads with forking and inter-thread communication
US5812811A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1995 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Feb 3, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A central processing unit (CPU) in a computer that permits speculative parallel execution of more than one instruction thread. The CPU uses Fork-Suspend instructions that are added to the instruction set of the CPU, and are inserted in a program prior to run-time to delineate potential future threads for parallel execution. The CPU has an instruction cache with one or more instruction cache ports, a bank of one or more program counters, a bank of one or more dispatchers, a thread management unit that handles inter-thread communications and discards future threads that violate dependencies, a set of architectural registers common to all threads, and a scheduler that schedules parallel execution of the instructions on one or more functional units in the CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.