Timer bus structure for an integrated circuit
US5812833A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1995 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Nov 13, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
I/O control modules (25-29) include a timer bus (71, 72) which may be segmented anywhere along its length. As a result, the channels (86, 87) are partitioned by each timer bus (71, 72) into separate blocks of channels (86, 87) which are provided with access to different timebases by their respective timer bus (71, 72). The channels within one timer bus block (e.g. 86) can be used to perform different function(s) with the potential for no loss of resolution because each channel in a timer bus block (e.g. 86) can concurrently receive the same timebase value from its corresponding timer bus (71). In one embodiment, one end of each timer bus (71, 72) is delineated by a master timer bus control channel (61, 63), and the other end of the timer bus is delineated by a slave timer bus control channel (62, 64).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.