Efficient ROM and PLA recoding to save chip area
US5812856A · kind A · utility
3Cited by
7References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 23, 1997 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Jun 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
DSP size and cost can be reduced by shrinking the program ROM and opcode interpreter (e.g., PLA) to store and recognize only #OC unique opcodes from within the total available opcodes for the DSP. The minimum opcode length M is the smallest integer satisfying 2.sup.M .gtoreq.#OC. It is preferred to choose an opcode length M'>M so that the total chip area occupied by the ROM plus PLA is minimized without loss of chip performance. By converting 24 bit opcodes to 16 bit opcodes for M=12 and M'=16, the combined program ROM and PLA areas are reduced by .about.1/3rd and the overall DSP is significantly smaller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.