Cache memory system with simultaneous access of cache and main memories
US5813030A · kind A · utility
13Cited by
23References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 2, 1997 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | May 2, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system includes a cache memory system which receives an address and a memory request from a processor. Simultaneously, information is accessed responsive to the address from a main memory and from a cache memory. During access of the information from the main memory and cache memory, it is determined whether the desired information is stored in the cache memory. If so, the information is output from the cache memory; if not, the information is output from the main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.