Duty cycled control implemented within a frequency synthesizer
US5815042A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 1996 |
| Grant date | Sep 29, 1998 |
| Priority date | — |
| Expiry date | Apr 18, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable frequency synthesizer comprised of a phase locked loop (PLL) including a current controlled oscillator (ICO), a level translator for receiving output signals from the ICO wherein the output signals have a finite slew rate, a reference source of signals, a phase-frequency detector for receiving signals from the reference source and output signals generated by the level translator and for providing pulse signals to the ICO having pulse widths which are directly proportional to phase difference between the signals from the reference source and the output signals from the level translator, and apparatus for varying the slew rate of the output signals from the ICO wherein the duty cycle and thus the frequency of output signals of the level translator may be varied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.