Voltage multiplexed chip I/O for multi-chip modules
US5815100A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1996 |
| Grant date | Sep 29, 1998 |
| Priority date | — |
| Expiry date | Jun 4, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1732
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electrical interconnect between a plurality of output nodes of a first integrated circuit (IC) and a plurality of input nodes of a second IC, the interconnect. A first bond pad located on the first integrated circuit is coupled to the output nodes. A second bond pad located on the second integrated circuit is coupled to the input nodes. A first digital-to-analog converter located on the first integrated circuit and having an output coupled to the first bond pad receives a plurality of binary inputs from the output nodes of the first integrated circuit. A first analog-to-digital converter is located on the second integrated circuit and coupled to the second bond pad and has an output line coupled to each of the plurality of input nodes of the second IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.