Tiled memory addressing with programmable tile dimensions
US5815168A · kind A · utility
48Cited by
18References
32Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 21, 1995 |
| Grant date | Sep 29, 1998 |
| Priority date | — |
| Expiry date | Dec 21, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/122
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display controller for a computer or the like stored display data in a tiled format in a display memory. Tile shape may be dynamically altered depending upon display mode (resolution, pixel depth, or the like) or other display factors. Tile shape (height versus width) may be optimized for different types of display (e.g., video, text, graphics, or the like). A display memory address conversion apparatus may receive pixel position data (e.g., from a BIT BLT engine or the like) and tile shape data and convert pixel position data to a tiled display memory address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.