Semiconductor memory device
US5815449A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 15, 1997 |
| Grant date | Sep 29, 1998 |
| Priority date | — |
| Expiry date | Sep 15, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a nonvolatile semiconductor memory device, upon receiving a defective cell address detection signal HIT, the read-out potential node (VSA NODE 1, VSA NODE 2) and the reference potential node (VREF NODE 1, VREF NODE 2) are equalized to shorten the read-out time required for reading the redundancy memory cell. Furthermore, in a nonvolatile semiconductor memory device having an ATD circuit, the equalizing times of the read-out potential node and the reference potential node are separately set to shorten the read-out time required for reading the main memory cell. With these features, there is overcome a disadvantage in prior art that the read-out time required for reading the redundancy memory cell is longer than the read-out time required for reading the main memory cell due to the slow rising of the HIT signal for detecting the defective cell address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.