Synchronous semiconductor memory device and synchronous memory module
US5815462A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Feb 12, 1997 |
| Grant date | Sep 29, 1998 |
| Priority date | — |
| Expiry date | Feb 12, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first clock signal for controlling the inputting of an external signal and for controlling internal operation and a second clock signal for controlling data output are applied to separate clock input nodes, respectively. Data output timing with respect to the first clock signal can be adjusted and thus clock access time and data hold time can be adjusted. Internal data read path is pipelined to include a first transfer gate responsive to the first clock signal for transferring internal read data and a second transfer gate responsive to the second clock signal for transferring the internal read data from the first transfer gate for external outputting through an output buffer. A synchronous semiconductor memory device is provided capable of setting clock access time and data hold time at the optimal values depending on the application and of reducing the clock access time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.