Verification of accesses in a functional model of a speculative out-of-order computer system
US5815688A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 9, 1996 |
| Grant date | Sep 29, 1998 |
| Priority date | — |
| Expiry date | Oct 9, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for testing and verifying the correctness of cache accesses on a model or implementation of a processor that performs speculative and or out-of-order instruction execution. For each behavioral model of a processor under test in a simulation system, an architectural model is created that is fed the same instruction stream and system bus stimulus. The architectural model is capable of correctly and independently executing the instruction stream. The cache and TLB state of the architectural model are kept synchronous with those of the behavioral model under test. Cache synchronization is achieved by reporting, matching and verifying all speculative cache activity and all out-of-order cache accesses, move-ins and move-outs by the behavioral model as it occurs rather than in natural program order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.