System for handling interrupts in a computer system using asic reset input line coupled to set of status circuits for presetting values in the status circuits
US5815733A · kind A · utility
25Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 1, 1996 |
| Grant date | Sep 29, 1998 |
| Priority date | — |
| Expiry date | Feb 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides an interrupt register for handling interrupt requests received from external devices at a common interrupt terminal of a CPU. The invention provides inputs, outputs, and storage means as part of the interrupt register. The interrupt register inputs and outputs are used for communication with both the external devices and CPU to prevent mishandling of the interrupt requests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.