Thin film transistor and method for fabricating thereof
US5818067A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 1997 |
| Grant date | Oct 6, 1998 |
| Priority date | — |
| Expiry date | Nov 5, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6717
Abstract
This invention relates to thin film transistors having a sloped drain region suitable for high integrated elements and the method for fabricating the same. The thin film transistor comprising a substrate, a gate pole formed on the central part of the substrate, a semiconductor layer formed to surround the gate pole on the substrate, a side wall spacer formed at one side of the gate pole on the semiconductor layer, and high density impurity regions formed in the semiconductor layer on both sides of the gate pole. The method for fabricating a TFT comprising steps for forming a gate pole on the central part of a substrate, forming a gate insulation film and a semiconductor layer successively on all over the surface of the substrate, forming a side wall spacer only at one side of the gate pole on the semiconductor layer, and forming high density impurity regions in the semiconductor layer on both sides of the gate by ion injecting impurity ions into the semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.