Integrated circuit output buffers having duration sensitive output voltage, and related buffering methods
US5818258A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 12, 1996 |
| Grant date | Oct 6, 1998 |
| Priority date | — |
| Expiry date | Sep 12, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Integrated circuit output buffers and buffering methods are responsive to the input logic signal frequency to produce higher output voltages for lower frequency logic signals and lower output voltages for higher frequency logic signals. Stated differently, the output level is not raised when the data signal is provided at high speed so that power consumption and noise malfunctions may be reduced. An integrated circuit output buffer includes a driver circuit which is responsive to an input logic signal which is at a first input logic value, to drive an output terminal to a first output logic value. The driver circuit is responsive to the input logic signal at a second logic value which is logically complementary to the first input logic value, to drive the output terminal to a second output logic value at a first voltage level, where the second output logic value is logically complementary to the first output logic value. The integrated circuit buffer also includes a time dependent driver boosting circuit, which is responsive to the input logic signal being at the second input logic value for a predetermined time, to boost the driver circuit to drive the output terminal to the secon…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.