High power FET switch
US5818283A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 1996 |
| Grant date | Oct 6, 1998 |
| Priority date | — |
| Expiry date | Jul 11, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/102
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an FET switch for controllably allowing and inhibiting passage of an input signal in ON state and OFF state, respectively, FETs are connected in a multi-stage configuration. A control voltage adjusting circuit is connected between a gate and one of a drain and a source of each FET. The control voltage adjusting circuit adjusts a gate-source voltage so as to follow the variation of a drain-source voltage. The input voltage applied to the FET switch in OFF state is divided by the plurality of FETs. Since the variation of the gate-source voltage follows the variation of the drain-source voltage, the FET switch is hardly influenced by an amplitude of the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.