Digital demodulator for a phase-modulated signal
US5818297A · kind A · utility
Assignees
Inventor
Key dates
| Filing date | May 13, 1997 |
| Grant date | Oct 6, 1998 |
| Priority date | — |
| Expiry date | May 13, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2276
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The demodulator is for processing a signal having a carrier modulated by (0, .pi.) phase shifts and sampled at a rate that is at least twice the frequency of the carrier co. It comprises, in cascade: a first multiplier for squaring successive samples e(t), a phase locked loop adjusted to the frequency of the carrier, thereby performing programmable digital filtering; a divider for dividing the frequency by two, reconstituting the carrier from the output of the phase locked loop; a second multiplier receiving the sampled input signal and the output signal from the divider and an output lowpass digital filter. A phase adjustment circuit is placed upstream of one of the inputs of the second multiplier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.