MPEG compatible decoder including a dual stage data reduction network
US5818530A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 1996 |
| Grant date | Oct 6, 1998 |
| Priority date | — |
| Expiry date | Jun 19, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/426
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A television receiver with an MPEG decoder is configurable for full high definition decoding and display, or reduced cost lower definition display. The MPEG decoder (10-33) uses a controllable dual-mode data reduction network selectively employing horizontal detail reduction (29) and data re-compression (30) between the decoder and the decoder frame memory (20) from which image information to be displayed (27) is derived. The amount of data reduction is manufacturer selected in accordance with the resolution of the display device, e.g., equal to or less than high definition resolution. The frame memory size is also manufacturer selected in accordance with the resolution of the display device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.