Active matrix substrate and manufacturing method of the same
US5818549A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1997 |
| Grant date | Oct 6, 1998 |
| Priority date | — |
| Expiry date | Mar 3, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/00
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
First and second gate insulating films, a semiconductor layer made of a-Si(i), and an etching stopper layer are formed to cover a gate electrode on a glass substrate. A drain electrode side contact layer and a source electrode side contact layer are made out of a-Si(n.sup.+) in such a manner to be cut off on the etching stopper layer. A disconnection preventing a-Si(n.sup.+) wire is formed below a source wire in its longitudinal direction, and atop of which a pixel electrode is formed. Since the disconnection preventing a-Si(n.sup.+) wire and source electrode side contact layer are spaced apart, static-induced characteristics deterioration of TFT and the point and line defects during the substrate fabrication sequence can be eliminated and the non-defective ratio of the display device can be improved drastically.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.