Processor for performing shift operations on packed data
US5818739A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1997 |
| Grant date | Oct 6, 1998 |
| Priority date | — |
| Expiry date | Apr 17, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a fist location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data shift operation is to be performed. The processor further includes a circuit being coupled to the decoder. The circuit is for shifting a first packed data being stored at the first location by a value being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.