Non-volatile semiconductor memory device capable of high speed programming/erasure
US5818761A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 1997 |
| Grant date | Oct 6, 1998 |
| Priority date | — |
| Expiry date | Jul 18, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3468
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To a column line to which a selected memory cell is connected, a write bias voltage is supplied through a selection gate transistor having different channel conductivity type than the memory cell transistor. Current drivability of the selection gate transistor is adapted to be larger than a leak current of the memory cell and to supply a current smaller than the channel current when a channel is formed in one aspect. When a verifying voltage is applied to the selected word line, a large channel current flows when a channel is formed, potential of a subbit line is changed accordingly, and programming is suppressed. In another aspect, the selection gate transistor serves as a constant current source to make the programming speed of the memory cells constant. Thus distribution of threshold values after programming can be made narrow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.