Galois field multiplier for Reed-Solomon decoder
US5818855A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 18, 1997 |
| Grant date | Oct 6, 1998 |
| Priority date | — |
| Expiry date | Feb 18, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/724
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Reed-Solomon decoder includes an optimized Galois Field multiplication circuit. The circuit has a plurality of multipliers, connected in a linear chain, wherein a first multiplicand of the first multiplier is the magnitude A, and the second multiplicand is a constant. The circuit operates on a linear combination of alpha values that sum to .alpha..sup.j, each multiplier in the chain generating a succeeding alpha value. A plurality of selectors enable the outputs of the multipliers according to the magnitude .alpha..sup.j. An addition circuit, preferably realized as a logical network of XOR gates, is connected to the selectors for adding the enabled outputs of the multipliers to form the final product.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.