Generation of phase shifted clock using selected multi-level reference clock waveform to select output clock phase
US5818889A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 12, 1992 |
| Grant date | Oct 6, 1998 |
| Priority date | — |
| Expiry date | Aug 12, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A phase shifter system includes a number of gates 40, 41 for receiving a reference clock and a number of gates 30-33 for receiving a predicted desired phase. The reference clock is manipulated by latches 43-46 and further gates 48, 49 so as to produce quadrature derivatives and these are connected across the resistor chain R1-R9 to produce multilevel waveforms, the steps being selected by selector 36 connected to the resistor nodes under the control of the predicted phase information from gates 30-33. Filtering and reshaping via comparator 50 provides an output clock pulse of desired phase. The output clock can be used to provide phase control in a transmission/reception system on a communications network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.